Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra- thin interfacial InGaZnO:N layer
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Effects of Interface and Bulk States on the Stability of Amorphous InGaZnO Thin Film Transistors under Gate Bias and Temperature Stress
The gate bias and temperature instability of InGaZnO TFTs were improved by adopting double stacked channel layer (DSCL). The mechanism of Vth shift under stress was studied by this structure. An interface with of less oxygen plasma damaging and lower oxygen vacancies in bulk were achieved by DSCL, resulting in a higher stability of Vth.
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